1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.
2. Description of the Related Art
Electrically erasable nonvolatile semiconductor memory devices need to have a high-speed writing and erasing characteristic and an excellent charge retention characteristic.
U.S. Pat. No. 6,784,484 proposes a tunnel insulating film having a structure in which a high dielectric constant film is sandwiched between low dielectric constant films. This structure makes it possible to achieve the high-speed writing and erasing characteristic and the excellent charge retention characteristic.
However, this proposal discloses a method of forming a high dielectric constant film but not a method of forming a low dielectric constant film. A method of forming a tunnel insulating film is an important factor for obtaining a high-performance tunnel insulating film excellent in film quality and interface characteristic. Accordingly, the above proposal cannot provide a tunnel insulating film excellent in film quality and interface characteristic. This results in difficulty in obtaining a high-performance nonvolatile memory.
With a continuous reduction in the size of elements in the nonvolatile memory, the parasitic capacitance between adjacent floating gates becomes a major problem. The parasitic capacitance between the floating gates disadvantageously increases an operating voltage and induces frequent malfunctioning. The structure disclosed in the above proposal cannot reduce the parasitic capacitance between the floating gates. This results in difficulty in obtaining a high-performance nonvolatile memory.
The structure in which a high dielectric constant film is sandwiched between low dielectric constant films has thus been proposed to achieve the high-speed writing and erasing characteristic and the excellent charge retention characteristic. However, the proposed structure cannot provide a tunnel insulating film excellent in film quality and interface characteristic. This results in difficulty in obtaining a high-performance nonvolatile memory. The proposed structure also fails to reduce the parasitic capacitance between the floating gates. This also results in difficulty in obtaining a high-performance nonvolatile memory.